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? semiconductor components industries, llc, 2011 april, 2011 ? rev. 3 1 publication order number: cm3202 ? 00/d CM3202-00 ddr vddq and vtt termination voltage regulator product description the cm3202 ? 00 is a dual ? output low noise linear regulator designed to meet sstl ? 2 and sstl ? 3 specifications for ddr ? sdram v ddq supply and termination voltage v tt supply. with integrated power mosfet?s, the cm3202 ? 00 can source up to 2 a of vddq continuous current, and source or sink up to 2 a vtt continuous current. the typical dropout voltage for vddq is 500 mv at 2 a load current. the cm3202 ? 00 provides fast response to transient load changes. load regulation is excellent, from no load to full load. it also has built ? in over ? current limits and thermal shutdown at 170 c. the cm3202 ? 00 supports suspend ? to ? ram (str) and acpi compliance with shutdown mode which tri ? states v tt to minimize quiescent system current. the cm3202 ? 00 is packaged in an easy ? to ? use wdfn8. low thermal resistance allows it to withstand high power dissipation at 85 c ambient. it operates over the industrial ambient temperature range of ?40 c to 85 c. features ? two linear regulators ? maximum 2 a current from vddq ? source and sink up to 2 a vtt current ? 1.7 v to 2.8 v adjustable v ddq output voltage ? 500 mv typical vddq dropout voltage at 2 a ? v tt tracking at 50% of vddq ? excellent load and line regulation, low noise ? fast transient response ? meet jedec ddr ? i and ddr ? ii memory power spec. ? linear regulator design requires no inductors and has low external component count ? integrated power mosfets ? dual purpose adj/shutdown pin ? built ? in over ? current limit and thermal shutdown for vddq and vtt ? fast transient response ? low quiescent current ? these devices are pb ? free and are rohs compliant applications ? ddr memory and active termination buses ? desktop computers, servers ? residential and enterprise gateways ? dsl modems ? routers and switchers ? dvd recorders ? 3d agp cards ? lcd tv and stb marking diagram device package shipping ? ordering information http://onsemi.com cm3202 ? 00de wdfn8 (pb ? free) 3000/tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d. cm320 200de = cm3202 ? 00de cm320 200de wdfn8 de suffix case 511bh 1
cm3202 ? 00 http://onsemi.com 2 typical application v in = 3.3 v to 3.6 v c in 220 f/ 10 v c tt 4.7 f 10 v cer v tt = 1.25 v/2 a vin 1 2 3 4 nc vtt nc cm3202 vddq adjsd gnd gnd 8 7 6 5 s/d r1 10 k v ddq = 2.5 v/2 a chip set vddq c ddq dl0 dln vddq rt0 rtn ddr ref memory v tt 0.1 f/10 v cer 4.7 f 10 v cer 220 f/ 10 v 4.7 f 10 v, cer 220 f/ 10 v 1 k 1.25 v, 2.5 a v ref r2 10 k functional block diagram - + - + vin adjsd vddq v tt gnd current limit otp & shutdown uvlo & bandgap cm3202 - + - + current limit 1.22 v 0.49* vddq 0.51* vddq current limit
cm3202 ? 00 http://onsemi.com 3 package / pinout diagrams top view (pins down view) cm320 200de thermal pad pin 1 marking vin nc vtt nc 1 2 3 4 vddq adjsd gnd gnd 8 7 6 5 8 ? lead wdfn package cm3202 ? 00de gnd pad 1 2 3 4 8 7 6 5 bottom view (pins up view) table 1. pin descriptions lead(s) name description 1 vin input supply voltage pin. bypass with a 220 f capacitor to gnd. 2 nc not internally connected. for better heat flow, connect to gnd (exposed pad). 3 vtt v tt regulator output pin, which is preset to 50% of v ddq . 4 nc not internally connected. for better heat flow, connect to gnd (exposed pad). 5 gnd ground pin (analog). 6 gnd ground pin (power). 7 adjsd this pin is for v ddq output voltage adjustment. it is available as long as v ddq is enabled. during manual/thermal shutdown, it is tightened to gnd. the v ddq output voltage is set using an external resistor divider connected to adjsd: v ddq = 1.25 v ((r1 + r2) / r2) where r1 is the upper resistor and r2 is the ground ? side resistor. in addition, the adjsd pin functions as a shutdown pin. when adjsd voltage is higher than 2.7 v (shdn_h), the circuit is in shutdown mode. when adjsd voltage is below 1.5 v (shdn_l), both vddq and vtt are enabled. a low ? leakage schottky diode in series with adjsd pin is recommended to avoid interference with the voltage adjustment setting. 8 vddq v ddq regulator output voltage pin. epad gnd the backside exposed pad which serves as the package heatsink. must be connected to gnd.
cm3202 ? 00 http://onsemi.com 4 specifications table 2. absolute maximum ratings parameter rating units vin to gnd [gnd ? 0.3] to +6.0 v pin voltages v ddq , v tt to gnd adjsd to gnd [gnd ? 0.3] to +6.0 [gnd ? 0.3] to +6.0 v output current vddq / vtt, continuous (note 1) vddq / vtt, peak vddq source + vtt source 2.0 / 2.0 2.8 / 2.8 3 a temperature operating ambient operating junction storage ?40 to +85 ?40 to +170 ?40 to +150 c thermal resistance, r ja (note 2) wdfn8, 3 mm x 3 mm 55 c / w continuous power dissipation (note 2) wdfn8, t a = 25 c / 85 c 2.6 / 1.5 w esd protection (hbm) 2000 v lead temperature (soldering, 10 sec) 300 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. despite the fact that the device is designed to handle large continuous/peak output currents, it is not capable of handling t hese under all conditions. limited by the package thermal resistance, the maximum output current of the device cannot exceed the limit imposed by the maximum power dissipation value. 2. measured with the package using a 4 in 2 / 2 layers pcb with thermal vias. table 3. standard operating conditions parameter rating units ambient operating temperature range ?40 to +85 c vddq regulator ddr ? 1 supply voltage, vin load current, continuous load current, peak (1 s) c ddq 3.1 to 3.6 0 to 2 2.5 220 v a a f vtt regulator ddr ? 1 supply voltage, vin load current, continuous load current, peak (1 s) c tt 3.1 to 3.6 0 to 2.0 2.50 220 v a a f v in supply voltage range 3.10 to 3.60 v vddq source + vtt source load current, continuous load current, peak (1 s) 2.5 3.5 a junction operating temperature range ?40 to +150 c
cm3202 ? 00 http://onsemi.com 5 specifications (cont?d) table 4. electrical operating characteristics (note 1) symbol parameter conditions min typ max units general i q quiescent current i ddq = 0, i tt = 0 8 15 ma i shdn shutdown current v adjsd = 3.3 v (shutdown) 0.1 0.5 ma shdn_h adjsd logic high (note 2) 2.7 v shdn_l adjsd logic low 1.50 v uvlo under ? voltage lockout hysteresis = 100 mv 2.40 2.70 2.90 v t over thermal shdn threshold 150 170 c t hys thermal shdn hysteresis 50 c tempco v ddq , v tt tempco 150 ppm/ c vddq regulator v ddq def vddq output voltage i ddq = 100 ma 2.450 2.500 2.550 v v ddq load vddq load regulation 10 ma i ddq 2 a (note 3) 10 25 mv v ddq line vddq line regulation 3.1 v v in 3.6 v, i ddq = 0.1 a 5 25 mv v drop vddq dropout voltage i ddq = 2 a (note 4) 500 mv i adj adjsd bias current 0.8 3.0 a i ddq lim vddq current limit 2.0 2.5 a vtt regulator v tt def vtt output voltage i tt = 100 ma 1.225 1.250 1.275 v v tt load vtt load regulation source, 0 i tt 2 a (note 3) sink, ? 2a i tt 0 (note 3) ?30 10 ?10 30 mv v tt line vtt line regulation 3.1 v v in 3.6 v, i tt = 0.1 a 5 15 mv i tt lim itt current limit source / sink (note 3) 2.0 2.5 a i vtt off vtt shutdown leakage current thermal shutdown enabled 10 a 1. v in = 3.3 v, v ddq = 2.50 v, v tt = 1.25 v (default values), c ddq = c tt = 47 f, t a = 25 c unless otherwise specified. 2. he shdn logic high value is normally satisfied for full input voltage range by using a low leakage current (bellow 1 a). schottky diode at adjsd control pin. 3. load and line regulation are measured at constant junction temperature by using pulse testing with a low duty cycle. changes in output voltage due to heating effects must be taken into account separately. load and line regulation values are guaranteed up to the maximum power dissipation. 4. dropout voltage is input to output voltage differential at which output voltage has dropped 100 mv from the nominal value obtained at 3.3 v input. it depends on load current and junction temperature.
cm3202 ? 00 http://onsemi.com 6 typical operating characteristics 0. 75 0. 85 0. 95 1. 05 1. 15 1. 25 1. 35 1. 45 1. 55 1. 65 1.5?1.75?2?2.25 2.5 2.75 3 3.25 2.490 2.495 2. 500 2.505 2.510 ? 40 ? 20 0 20 40 60 80 100 120 140 0 0.5 1.0 1.5 2.0 2.5 0 1.0 2.0 3.0 4.0 0 100 200 300 400 500 600 0 0.5 1.0 1.5 2.0 2.5 3.0 0 0.5 1.0 1.5 2.0 2.5 temperature ( c) vddq (v) vddq vs. temperature vtt vs. vddq vddq (v) vtt (v) vddq vs. load current iddq (a) vddq (v) v in = 3.3 v t a = 25 c vddq dropout vs. iddq iddq (a) dropout voltage (mv) t a = 25 c vtt vs. load current itt (a) vtt (v) startup into full load time (1 ms/div) uvlo vin 2 v/div vtt 1 v/div vin 2 v/div vddq 1 v/div 0 1.0 2.0 3.0 4.0
cm3202 ? 00 http://onsemi.com 7 typical operating characteristics (cont?d) v in i ddq 0.5a/div v ddq 0.1v/div i tt 0.5a/div v tt 0.1v/div time (0.2 ms/div) -0.75a vddq transient response vtt transient response v in = 3.3v time (0.2 ms/div) application information powering ddr memory double ? data ? rate (ddr) memory has provided a huge step in performance for personal computers, servers and graphic systems. as is apparent in its name, ddr operates at double the data rate of earlier ram, with two memory accesses per cycle versus one. ddr sdram?s transmit data at both the rising and falling edges of the memory bus clock. ddr?s use of stub series terminated logic (sstl) topology improves noise immunity and power ? supply rejection, while reducing power dissipation. to achieve this performance improvement, ddr requires more complex power management architecture than previous ram technology. unlike the conventional dram technology, ddr sdram uses differential inputs and a reference voltage for all interface signals. this increases the data bus bandwidth, and lowers the system power consumption. power consumption is reduced by lower operating voltage, a lower signal voltage swing associated with stub series terminated logic (sstl_2), and by the use of a termination voltage, v tt . sstl_2 is an industry standard defined in jedec document jesd8 ? 9. sstl_2 maintains high ? speed data bus signal integrity by reducing transmission reflections. jedec further defines the ddr sdram specification in jesd79c. ddr memory requires three tightly regulated voltages: v ddq , v tt , and v ref (see t ypical ddr terminations, class ii). in a typical sstl_2 receiver, the higher current v ddq supply voltage is normally 2.5 v with a tolerance of 200 mv. the active bus termination voltage, v tt , is half of v ddq . v ref is a reference voltage that tracks half of v ddq, 1%, and is compared with the v tt terminated signal at the receiver. v tt must be within 40 mv of v ref figure 1. typical ddr terminations, class ii ? + vddq vtt (=vddq/2) vddq vref (=vddq/2) receiver transmitter line rs = 25 rt = 25
cm3202 ? 00 http://onsemi.com 8 application information (cont?d) the vtt power requirement is proportional to the number of data lines and the resistance of the termination resistor, but does not vary with memory size. in a typical ddr data bus system each data line termination may momentarily consume 16.2 ma to achieve the 405 mv minimum over v tt needed at the receiver: i terminaton 405 mv rt (25 ) 16.2 ma a typical 64 mbyte sstl ? 2 memory system, with 128 terminated lines, has a worst ? case maximum v tt supply current up to 2.07 a. however, a ddr memory system is dynamic, and the theoretical peak currents only occur for short durations, if they ever occur at all. these high current peaks can be handled by the v tt external capacitor. in a real memory system, the continuous average v tt current level in normal operation is less than 200 ma. the vddq power supply, in addition to supplying current to the memory banks, could also supply current to controllers and other circuitry. the current level typically stays within a range of 0.5 a to 1 a, with peaks up to 2 a or more, depending on memory size and the computing operations being performed. the tight tracking requirements and the need for v tt to sink, as well as source, current provide unique challenges for powering ddr sdram. cm3202 ? 00 regulator the cm3202 ? 00 dual output linear regulator provides all of the power requirements of ddr memory by combining two linear regulators into a single tdfn ? 8 package. vddq regulator can supply up to 2 a current, and the two ? quadrant v tt termination regulator has current sink and source capability to 2 a. the vddq linear regulator uses a pmos pass element for a very low dropout voltage, typically 500 mv at a 2 a output. the output voltage of v ddq can be set by an external voltage divider. the use of regulators for both the upper and lower side of the vddq output allows a fast transient response to any change of the load, from high current to low current or inversely. the second output, v tt , is regulated at v ddq /2 by an internal resistor divider. same as vddq, vtt has the same fast transient response to load change in both directions. the v tt regulator can source, as well as sink, up to 2 a current. the cm3202 ? 00 is designed for optimal operation from a nominal 3.3 vdc bus, but can work with vin as high as 5 v. when operating at higher vin voltages, attention must be given to the increased package power dissipation and proportionally increased heat generation. v ref is typically routed to inputs with high impedance, such as a comparator, with little current draw. an adequate v ref can be created with a simple voltage divider of precision, matched resistors from v ddq to ground. a small ceramic bypass capacitor can also be added for improved noise performance. input and output capacitors the cm3202 ? 00 requires that at least a 220 f electrolytic capacitor be located near the v in pin for stability and to maintain the input bus voltage during load transients. an additional 4.7 f ceramic capacitor between the v in and the gnd, located as close as possible to those pins, is recommended to ensure stability. at a minimum of a 220 f electrolytic capacitor is recommended for the v ddq output. an additional 4.7 f ceramic capacitor between the v ddq and gnd, located very close to those pins, is recommended. at a minimum of a 220 f electrolytic capacitor is recommended for the v tt output. this capacitor should have low esr to achieve best output transient response. sp or oscon capacitors provide low esr at high frequency, and thus are a good choice. in addition, place a 4.7 f ceramic capacitor between the v tt pin and gnd, located very close to those pins. the total esr must be low enough to keep the transient within the v tt window of 40 mv during the transition for source to sink. an average current step of 0.5 a requires: esr 40 mv 1 a 40 m both outputs will remain stable and in regulation even during light or no load conditions.
cm3202 ? 00 http://onsemi.com 9 application information (cont?d) adjusting vddq output voltage the cm3202 ? 00 internal bandgap reference is set at 1.25 v. the v ddq voltage is adjustable by using a resistor divider, r1 and r2: v ddq v adj r 1 r 2 r 2 where v adj = 1.25 v. for best regulator stability, we recommend that r 1 and r 2 not exceed 10 k each. shutdown adjsd also serves as a shutdown pin. when this is pulled high (shdn_h), both the vddq and the vtt outputs tri ? state and could sink/source less than 10 a. during shutdown, the quiescent current is reduced to less than 0.5 ma, independent of output load. it is recommended that a low leakage schottky diode be placed between the adjsd pin and an external shutdown signal to prevent interference with the adj pin?s normal operation. when the diode anode is pulled low, or left open, the cm3202 ? 00 is again enabled. current limit, foldback and over ? temperature protection the cm3202 ? 00 features internal current limiting with thermal protection. during normal operation, v ddq limits the output current to approximately 2 a and v tt limits the output current to approximately 2 a. when v tt is current limiting into a hard short circuit, the output current folds back to a lower level, about 1 a, until the over ? current condition ends. while current limiting is designed to prevent gross device failure, care should be taken not to exceed the power dissipation ratings of the package. if the junction temperature of the device exceeds 170 c (typical), the thermal protection circuitry triggers and tri ? states both vddq and vtt outputs. once the junction temperature has cooled to below about 120 c the cm3202 ? 00 returns to normal operation. thermal considerations typical thermal characteristics the overall junction to ambient thermal resistance ( ja ) for device power dissipation (p d ) primarily consists of two paths in the series. the first path is the junction to the case ( jc ) which is defined by the package style and the second path is case to ambient ( ca ) thermal resistance which is dependent on board layout. the final operating junction temperature for any condition can be estimated by the following thermal equation: t junc t amb p d ( jc ) p d ( ca ) t amb p d ( ca ) when a cm3202 ? 00 using wdfn8 package is mounted on a double ? sided printed circuit board with four square inches of copper allocated for ?heat spreading,? the ja is approximately 55 c/w. based on the over temperature limit of 170 c with an ambient temperature of 85 c, the available power of the package will be: p d 170 c 85 c 55 c w 1.5 w
cm3202 ? 00 http://onsemi.com 10 application information (cont?d) pcb layout considerations thecm3202 ? 00 has a heat spreader attached to the bottom of the wdfn8 package in order for the heat to be transferred more easily from the package to the pcb. the heat spreader is a copper pad of dimensions just smaller than the package itself. by positioning the matching pad on the pcb top layer to connect to the spreader during the manufacturing, the heat will be transferred between the two pads. see the thermal layout, the cm3202 ? 00 shows the recommended pcb layout. please be noted that there are four vias on either side to allow the heat to dissipate into the ground and power planes on the inner laye rs of the pcb. vias can be placed underneath the chip, but this can be resulted in blocking of the solder. the ground and power planes need to be at least 2 square inches of copper by the vias. it also helps dissipation if the chip is positioned away from the edge of the pcb, and not near other heat ? dissipating devices. a good thermal link from the pcb pad to the rest of the pcb will assure the best heat transfer from the cm3202 ? 00 to ambient, ja , of approximately 55 c/w. figure 2. thermal layout for wdfn8 package vias ( 0. 3 mm diameter ) thermal pad solder mask pin solder mask top layer copper connects to heat spreader bottom layer ground plane top view
cm3202 ? 00 http://onsemi.com 11 package dimensions wdfn8, 3x3, 0.65p case 511bh ? 01 issue o notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.15 and 0.30 mm from terminal tip. 4. coplanarity applies to the exposed pad as well as the terminals. ??? ??? ??? a d e b c 0.10 pin one 2x reference 2x top view side view bottom view l d2 e2 c c 0.10 c 0.10 c 0.08 a1 seating plane 8x note 3 b 8x 0.10 c 0.05 c a b b dim min max millimeters a 0.70 0.80 a1 0.00 0.05 b 0.25 0.35 d 3.00 bsc d2 2.20 2.40 e 3.00 bsc e2 1.40 1.60 e 0.65 bsc l 0.20 0.40 1 4 8 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 0.65 pitch 1.66 3.30 1 dimensions: millimeters 0.53 8x note 4 0.40 8x detail a a3 0.20 ref a3 a detail b l1 detail a l alternate constructions ?? ?? ??? ??? 0.15 outline package e recommended k 0.45 ref 5 2.46 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 cm3202 ? 00/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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